This invention relates to an electronic design automation method and a device therefor and, in particular, to a design automation method of verifying the reliability in a semiconductor integrated circuit and a device therefor.
Generally, a design automation method of the type is widely used in designing and synthesizing a semiconductor integrated circuit and is also used to verify the reliability of the semiconductor integrated circuit from design information of the semiconductor integrated circuit.
In such methods of verifying the reliability of the semiconductor integrated circuit, electromigration of the semiconductor integrated circuit is selected as an object of verification in some instances while hot carrier effect of the semiconductor integrated circuit is selected as an object of verification in some other instances. The electromigration is a phenomenon which occurs when a thin film conductor is supplied with electric current having a high current density. Due to the electromigration, a cavity is produced in a wiring pattern and brings about an open circuit or a short-circuit between patterns. On the other hand, the hot carrier effect is a phenomenon that hot carriers are implanted and captured in an oxide film when a high electric field is applied. Generation of the hot carrier effect results in variation of a threshold voltage of a transistor or deterioration of conductance.
Therefore, the electromigration and the hot carrier effect must strictly be checked and verified upon designing the semiconductor integrated circuit.
As a conventional method which deals with the electromigration as an object of verification and which detects a portion having a potential risk of the electromigration, a verification method is disclosed in Japanese Unexamined Patent Publication (JP-A) No. 9-293765 (hereinafter referred to as Reference 1). In the verification method described in Reference 1, verification is made about whether or not a peak current density of an electric current flowing through a verification object, such as a wire, satisfies a limiting value of the peak current density determined by a design specification against the electromigration.
On the other hand, conventional methods directed to the hot carrier effect as an object of verification are described in Japanese Unexamined Patent Publication (JP-A) No. 9-292436 (hereinafter referred to as Reference 2) and Japanese Unexamined Patent Publication (JP-A) No. 9-330344 (hereinafter referred to as Reference 3). Reference 2 discloses a method of estimating the deterioration of the transistor due to the hot carriers and assuring the reliability about the timing throughout a desired lifespan. On the other hand, Reference 3 discloses a method of calculating an output load of each cell, calculating with reference to the output load thus calculated and reliability information of each cell a transistor life of each cell depending upon the hot carriers, and comparing the life with a reference value to verify the reliability of each cell.
In the present status, verification of the electromigration reference value and verification of the hot carrier effect reference value are separately executed. Specifically, the electromigration reference value is generally given by a limiting value of an electric current flowing through the wire while the hot carrier effect reference value is given by a limiting value of deterioration in a gate oxide film of an N-channel transistor.
The electromigration reference value and the hot carrier effect reference value are related to different objects different from each other and have different values different from each other. Therefore, in the present status, these reference values are converted into limiting value parameters of different formats quite different from each other and are subjected to verification by reliability verifying techniques different from each other.
Accordingly, with the conventional verification methods, the electromigration reference value and the hot carrier effect reference value must be individually verified as two separate steps. Since two verification results are obtained, it is necessary to refer to the two verification results upon feeding back verification errors to a design stage. This results in a complicated design work.
More specifically, design criteria for both factors show limiting values quite different from each other. If a verification error is present in at least one of them, it is necessary to modify the circuit. Thus, twice execution of the reliability verification is a serious disadvantage in the design work.
It is an object of this invention to provide a design automation method and device capable of verifying the reliability without separately verifying a plurality of verification objects in a plurality of steps.
It is another object of this invention to provide a logical synthesis tool capable of simultaneously verifying a plurality of verification objects.
According to one aspect of this invention, there is provided a design automation method for verifying by the use of a computer the reliability in a circuit represented by a logical level, the method comprising a step of selecting first and second verification factors for verifying the reliability of the circuit, a step of setting first and second limiting values related to the first and the second verification factors, respectively, a step of setting a combined limiting value common to the first and the second verification factors with reference to the first and the second limiting values, and a step of verifying by the use of the combined limiting value the reliability of the circuit represented by the logical level.
According to another aspect of this invention, there is provided a logical synthesis tool for synthesizing by the use of a computer a circuit represented by a logical level, the tool including a table holding first and second limiting values related to predetermined first and second factors, respectively, a table holding a combined limiting value obtained from the first and the second limiting values, and means for verifying and synthesizing by the use of the combined limiting value the circuit represented by a logical level.
According to still another aspect of this invention, there is provided a layout tool for inserting a wire and a buffer, the layout tool including a table storing limiting values related to factors different from one another, a table storing a combined limiting value calculated from the limiting values different from one another, and means for inserting the wire and the buffer with reference to the combined limiting value.
According to a different aspect of this invention, there is provided a recording medium for use in design and verification of a circuit represented by a logical level, the medium including a table related to a plurality of factors used in the design and the verification and means storing a procedure for combining the factors.